The present invention relates to a data transfer apparatus which transfers data between a peripheral device and the main storage unit, and more particularly to a data transfer apparatus which performs a direct access memory transfer.
Conventionally, when data is transferred in the direct memory access (hereinafter called DMA) transfer mode in which data is transferred from a peripheral device to the main storage unit without processor intervention, data is transferred from consecutive addresses in the address space of the peripheral device to consecutive addresses in the main storage unit. During this DMA transfer, data is read sequentially from the address space of the peripheral device, beginning with the start address, and is written sequentially into the address space of the main storage unit, beginning with the start address.
In contrast to the DMA transfer described above, data is sometimes transferred from the consecutive address space on a peripheral device to non-consecutive addresses in the main storage unit. For example, when image data generated by a character generator is transferred to non-consecutive addresses in the DMA transfer mode, the DMA controller adds the length of a gap in the destination address space to the value in the transfer destination register before starting the transfer. This allows the transfer destination address to be automatically updated even when there is a gap in the destination address space.
The conventional apparatus described above allows non-consecutive addresses to be used in the transfer destination, but not in the transfer source. The DMA transfer is executed within this limitation. However, when data is transferred from a peripheral device to the main storage unit, it is not always fastest to read data sequentially beginning with the start. This is because the peripheral device sometimes involves a delay factor such as a seek time. Instead, non-sequential reading, if accepted to some degree, enables data to be read faster as a whole in many cases.
On the other hand, the DMA data transfer, which is performed on the assumption that the transfer addresses are consecutive, does not ensure high speed system processing if each data transfer involves processor intervention.
It is an object of the present invention to provide a data transfer apparatus which accepts non-consecutive source data addresses to speed up data transfer while maintaining the DMA transfer framework.
In one preferred embodiment, the data transfer apparatus according to the present invention, provided for use in a direct memory access transfer in which data is transferred by calculating the physical address corresponding to the logical addresses of data to be transferred, resets the physical address upon detection that the logical addresses are not consecutive.